A synchronous digital hierarchy (SDH for short) network uses a hierarchical master-slave synchronization manner, that is, a primary reference clock (PRC for short) is used to control an entire network to be synchronous by using a synchronization link of a synchronization distribution network. The SDH network uses a series of hierarchical clocks, and a clock at each level is synchronous to a clock at an upper level or a clock at the same level. In the SDH network, a network element device at a current level uses, as a reference clock signal, a clock signal that is transmitted by a network element device at an upper level tracked by the network element device at the current level, and continues to transmit the reference clock signal to a network element device at a lower level of network element device. However, affected by complex factors, a frequency offset occurs in the reference clock signal in the transmission process; therefore, a network element device at each level needs to perform frequency offset detection on a reference clock signal.
In the prior art, whether a frequency offset occurs in a reference clock signal is detected in a manner of counting rising edges of the reference clock signal by using a clock signal output by a local crystal oscillator of a network element device. That is, a 19.44 MHz signal obtained by performing frequency halving on a 38.88 MHz signal output by the local crystal oscillator is used as a clock counter, periodically counting rising edges of a reference clock signal whose frequency is uniformly 8 kHz obtained by means of frequency division, and whether a frequency offset occurs in the reference clock signal is determined according to an actual count value on the counter and a preset value. However, a detection result obtained in this manner is inaccurate.